Title :
New CML latch structure for high speed prescaler design
Author :
Usama, Muhammad ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
This paper emphasizes on the design and analysis of current mode logic latches and their application in a frequency prescaler. Operation of a conventional CML latch is analyzed and a clock feedback structure is proposed for increased stability with reduced delay parameters. A low power design technique is presented for current mode logic frequency prescalers, which allows the master and slave latches to be merged together so that they use a single current source. This significantly reduces the power consumption and area and also offers lower terminal capacitances resulting in faster circuit operation.
Keywords :
circuit feedback; circuit stability; current-mode logic; digital phase locked loops; flip-flops; power consumption; prescalers; CML latch structure; PLL; circuit operation; clock feedback structure; current mode logic; frequency prescaler; high speed prescaler design; latches; low power design; power consumption reduction; reduced delay parameters; single current source; stability; terminal capacitances; Capacitance; Clocks; Delay; Energy consumption; Feedback; Frequency; Latches; Logic design; Master-slave; Stability analysis;
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
Print_ISBN :
0-7803-8253-6
DOI :
10.1109/CCECE.2004.1347586
