Role of temperature in process-induced charging damage in sub-micron CMOS transistors

High-field stressing of the gate oxide in sub-micron MOS transistors at various stress temperatures was used to simulate process-induced charging and latent damage creation during some of the processing steps. By studying degradation of transistor parameters in damaged devices it has been shown that the temperature of the wafer, at which devices experience charging effects, significantly enhances the amount of latent damage remaining in the Si-SiO₂ system after full processing. The increased density of neutral electron traps in the oxide and enhanced susceptibility of the interface to degradation in transistors, deteriorated at elevated temperatures, correlate with charge-to-breakdown reduction in both NMOS and PMOS transistors