Experimental investigation and design optimization guidelines of characteristic variability in silicon nanowire CMOS technology

Author

Zhuge, Jing ; Wang, Runsheng ; Huang, Ru ; Zou, Jibin ; Huang, Xin ; Kim, D.-W. ; Park, Donggun ; Zhang, Xing ; Yangyuan Wang

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2009

Firstpage

1

Lastpage

4

Abstract

In this paper, the characteristic variability in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) is experimentally studied. Variation sources in SNWTs are extracted for the first time, taking into account the strongly-confined geometry induced quantum effect, quasi-ballistic effects, as well as the parasitic quantum resistance at the interface of 1D channel and 3D wide S/D regions. The measured results show that with suppressed random dopant fluctuations (RDF) in the intrinsic channel, variations in radius (R) and metal-gate work function (WF) of SNWTs dominate both the threshold voltage and on-current fluctuations, and line-edge-roughness (LER) shows minor impact. The influence of the SNWT variation sources on SRAM performance is estimated and compared with planar devices. In addition to process variation, variation induced by random telegraph signal (RTS) noise in SNWTs is also investigated for the evaluation of SRAM cell operating window. Design optimization guidelines are given based on the SRAM variation analyzed results.

Keywords

CMOS integrated circuits; MOSFET; nanowires; SRAM cell operating window; SRAM performance; SRAM variation; characteristic variability; complementary metal-oxide-semiconductor; design optimization guidelines; gate-all-around silicon nanowire MOSFET; geometry induced quantum effect; intrinsic channel; line edge roughness; metal gate work function; metal-oxide-semiconductor field effect transistors; parasitic quantum resistance; quasiballistic effects; random telegraph signal noise; silicon nanowire CMOS technology; static random access memory; suppressed random dopant fluctuations; CMOS technology; Design optimization; Electrical resistance measurement; Fluctuations; Geometry; Guidelines; MOSFETs; Random access memory; Resource description framework; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424421

Filename

5424421