Title :
Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment
Author :
Hutin, L. ; Vinet, M. ; Poiroux, T. ; Le Royer, C. ; Previtali, B. ; Vizioz, C. ; Lafond, D. ; Morand, Y. ; Rivoire, M. ; Nemouchi, F. ; Carron, V. ; Billon, T. ; Deleonibus, S. ; Faynot, O.
Author_Institution :
LETI, CEA, Grenoble, France
Abstract :
We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20 nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22 nm nodes. We demonstrate pFET devices with promising electrical behavior (ION = 790 ¿A/¿m; IOFF = 60 nA/¿m @ VDS = -1.2 V; Lg = 30 nm), suitable for high performance applications. Excellent SCE control is also reported down to 30 nm (DIBL = 50 mV/V), through the use of Double Gate transistors.
Keywords :
MOSFET; Schottky gate field effect transistors; elemental semiconductors; erbium alloys; nanofabrication; nickel alloys; platinum alloys; semiconductor device models; semiconductor doping; silicon; silicon alloys; silicon-on-insulator; technology CAD (electronics); ytterbium alloys; ErSi; NiSi; PtSi; S-D metallizations; S-D-channel interfaces; TCAD simulation; YbSi; doping; double gate SOI CMOS; double gate transistors; dual metallic source and drain integration; electrical behavior; electrical characterization; metallic dopant segregated source-and-drain; n-MOSFET; p-MOSFET; planar single gate SOI CMOS; scalability assessment; short-channel effects control; single gate-on-ultrathin buried oxide device architecture; size 20 nm; size 30 nm; voltage -1.2 V; Decision support systems; Doping; Etching; Fabrication; MOSFETs; Metallization; Performance analysis; Scalability; Schottky barriers; Silicidation;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424425
