DocumentCode
1654620
Title
Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology
Author
Ortolland, C. ; Rosseel, E. ; Horiguchi, N. ; Kerner, C. ; Mertens, S. ; Kittl, J. ; Verleysen, E. ; Bender, H. ; Vandervost, W. ; Lauwers, A. ; Absil, P.P. ; Biesemans, S. ; Muthukrishnan, S. ; Srinivasan, S. ; Mayur, A.J. ; Schreutelkamp, R. ; Hoffmann,
Author_Institution
IMEC, Leuven, Belgium
fYear
2009
Firstpage
1
Lastpage
4
Abstract
A novel silicide formation technique using millisecond anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6 nm gate length reduction and more than 1 decade junction leakage improvement.
Keywords
CMOS integrated circuits; integrated circuit yield; laser beam annealing; nickel compounds; platinum compounds; NiPtSi; advanced low power platform CMOS technology; junction scaling; laser anneal; millisecond anneal; silicide film morphology; silicide formation technique; silicide yield improvement; CMOS technology; Degradation; High K dielectric materials; High-K gate dielectrics; Morphology; Nickel; Power lasers; Rapid thermal annealing; Silicides; Temperature;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location
Baltimore, MD
Print_ISBN
978-1-4244-5639-0
Electronic_ISBN
978-1-4244-5640-6
Type
conf
DOI
10.1109/IEDM.2009.5424428
Filename
5424428
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