Author :
Ortolland, C. ; Rosseel, E. ; Horiguchi, N. ; Kerner, C. ; Mertens, S. ; Kittl, J. ; Verleysen, E. ; Bender, H. ; Vandervost, W. ; Lauwers, A. ; Absil, P.P. ; Biesemans, S. ; Muthukrishnan, S. ; Srinivasan, S. ; Mayur, A.J. ; Schreutelkamp, R. ; Hoffmann,
Abstract :
A novel silicide formation technique using millisecond anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6 nm gate length reduction and more than 1 decade junction leakage improvement.
Keywords :
CMOS integrated circuits; integrated circuit yield; laser beam annealing; nickel compounds; platinum compounds; NiPtSi; advanced low power platform CMOS technology; junction scaling; laser anneal; millisecond anneal; silicide film morphology; silicide formation technique; silicide yield improvement; CMOS technology; Degradation; High K dielectric materials; High-K gate dielectrics; Morphology; Nickel; Power lasers; Rapid thermal annealing; Silicides; Temperature;
