The Novel Frame Boundary Detection and Fast Frame Synchronous Structure for 10 Gb/s Ethernet Phy FEC Sub-Layer VLSI Implementation

This paper presents the 10 Gb/s Ethernet Phy Forward Error Correction (FEC) sub-layer novel VLSI structure with the following 2 ideas: one is the frame boundary detecting methodology and the other is the fast frame synchronous structure. The first method increases the frame synchronizing speed by fully optimizing the candidate start position shift algorithm to accelerate the frame synchronization process; and the second structure increases the frame synchronizing speed by fully optimizing the structure of FEC decoder in the receiver to accelerate the frame synchronization process. The methods are used in a kind of network device to realize the FEC functions, and experimental result shows that the frame synchronizing speed is twice that of the conventional method, while the hardware overhead is very small.