A scaled 1.8 V, 0.18 μm gate length CMOS technology: device design and reliability considerations

Device design improvements for scaling to a high performance 1.8 V, 0.18 μm gate length CMOS technology are presented. nMOS with nominal I_drive(I_drive^nom)=55 μA/μm drive (with t_ox^acc=43 Å, t_ox^inv=49 Å from C-V at V_gb=-4, +2.5V), R_sd<280 Ω-μm, L_g^min (minimum gate length at I_off=1 nA/μm)=0.16 μm, and hot carrier lifetime ≫10 years is achieved. Increased As HDD dose, pocket implant, and RTA HDD anneal are required for simultaneous high I_drive^nom, high carrier velocity vs. DIBL, and L _g^min=0.16 μm. pMOS with L_g^min =0.16 μm and with I_drive^nom=220 μα/μm is achieved. BF₂ HDD plus RTA HDD anneal prior to sidewall deposition to eliminate interstitial enhanced B tail diffusion are utilized to form more abrupt pMOS HDD junctions. Super-steep retrograde (SSR) As channel profile reduces SCE and increases v_eff (and I_drive) vs. DIBL, but decreases v_eff (and I_drive) vs. I_off, compared to a non-SSR profile. pMOS (I_drive^nom)=220 μA/μm (with non-SSR profile) and nMOS I_drive^nom)=550 μA/μm result in a 30% improvement in speed for the 1.8 V, 0.18 μm technology compared to a prior 2.5 V, 0.25 μm technology