CMOS process design for minimization of IC power consumption using TCAD

Author

Schwerin, A.V. ; Schumann, D. ; Berthold, J.

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

fYear

1995

Firstpage

479

Lastpage

482

Abstract

CMOS low-voltage process design is presented as an example of industrial application of technology CAD. TCAD tools are used to evaluate G_P, the gain in power efficiency (i.e. battery lifetime) which is achievable by reduction of supply voltage (V_dd) with adaptation of threshold voltage (V_th) and gate length scaling for constant performance. The trade-off between leakage and active power depending on the IC properties is studied. Maximum G _P found for a 16 bit microprocessor with 32 kB on chip SRAM is about 7 for V_th of ±0.3V and V_dd of 1.3V

Keywords

CMOS digital integrated circuits; circuit CAD; circuit optimisation; integrated circuit design; microprocessor chips; minimisation; 1.3 V; 16 bit; 16 bit microprocessor; CMOS low-voltage process design; IC power consumption minimization; TCAD; battery lifetime; gate length scaling; leakage active power tradeoff; on chip SRAM; power efficiency; supply voltage reduction; technology CAD; threshold voltage; Batteries; CMOS integrated circuits; CMOS process; CMOS technology; Design automation; Electricity supply industry; Energy consumption; Performance gain; Process design; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499242

Filename

499242