Synchronous sequential circuits design using evolutionary algorithms

This paper explores the possibility of using genetic algorithms (GA) in automating the design of synchronous sequential circuits by employing multi objective optimization. The objective is to simultaneously design digital circuits with 100% functionality and to use the minimum number of logic devices and gates. Experiments are carried out to assess the performance of the proposed evolutionary algorithm to achieve an error-free circuit (3-bit up-counter) with minimum logic devices. In our experiments, two different techniques are proposed. The first method is to evolve the entire sequential circuit while the second aims at only evolving the combinational part of the sequential circuit. The results show the efficiency of the GA approach in synthesizing synchronous sequential circuits.