Finite element optimization of a MOSFET structure: the roll of interlayer material for residual stress reduction

Author

Ferreira, Paul ; Senez, Vincent ; Baccus, Bruno ; Varon, Jacques ; Lebailly, Jacques

Author_Institution

IEMN-ISEN, CNRS, Villeneuve d´´Ascq, France

fYear

1995

Firstpage

503

Lastpage

506

Abstract

Mechanical stress induced degradations of a MOS technology are investigated. Bidimensional stress simulations, coupled with electrical characterizations reveal the importance of the gate formation and TEOS deposition steps in the generation of mechanical stress. The use of a doped oxide as interlayer material between the polysilicon gate and the TEOS film is shown to significantly reduce the residual stress and associated electrical failures

Keywords

BIMOS integrated circuits; MOSFET; circuit optimisation; failure analysis; finite element analysis; integrated circuit reliability; internal stresses; isolation technology; semiconductor device reliability; semiconductor process modelling; BIMOS technology; DMOS structure; IMPACT-4 process simulator; LOCOS structure isolation; MOS technology; MOSFET structure; TEOS deposition; bidimensional stress simulations; doped oxide interlayer; electrical characterizations; electrical failures; finite element optimization; gate formation; interlayer material; mechanical stress induced degradation; polysilicon gate; residual stress reduction; Calibration; Character generation; Etching; Finite element methods; MOSFET circuits; Residual stresses; Temperature; Thermal degradation; Thermal stresses; Viscosity;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499248

Filename

499248