Chip design of a bandpass sigma-delta modulator

Author

Wu, Sau-Mou ; Liu, Rou-Yi ; Wu, Wei ; Chen, Che-Pin

Author_Institution

Electr. Eng. Dept., Yuan-Ze Univ., Chung-li, Taiwan

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1375

Abstract

This paper presents a bandpass sigma-delta modulator, which converts analog signals to the digital domain at the intermediate-frequency (IF) and can be used in new generation wireless communication receivers. The modulator is implemented in the TSMC 0.35 μm CMOS 2p4m process. The power supply is 3.3 V. Bandwidth is 200 kHz centered at 10.7 MHz. The sample frequency is 42.8 MHz. The peak SNR is about 72 dB. Power consumption is 68.942 mW. The modulator layout area is 890.62 μm ×801.61 μm

Keywords

CMOS integrated circuits; band-pass filters; integrated circuit layout; integrated circuit noise; sigma-delta modulation; switched capacitor filters; 0.35 micron; 10.7 MHz; 200 kHz; 3.3 V; 42.8 MHz; 68.942 mW; CMOS bandpass sigma-delta modulator; TSMC 0.35 μm CMOS 2p4m process; analog to digital signal conversion; bandpass SC filter; chip design; intermediate-frequency; modulator layout area; new generation wireless communication receiver; peak SNR; power consumption; power supply; sample frequency; Bandwidth; CMOS process; Chip scale packaging; Delta-sigma modulation; Digital modulation; Energy consumption; Frequency; Power supplies; Signal generators; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957470

Filename

957470