Low-power logic styles for full-adder circuits

Author

Quintana, J.M. ; Avedillo, M.J. ; Jiménez, R. ; Rodríguez-Villegas, E.

Author_Institution

Centro Nacional de Microelectron., Instituto de Microelectron. de Sevilla, Seville, Spain

Volume

3

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1417

Abstract

This paper contributes to a better knowledge of the behaviour of conventional CMOS and CPL full-adder circuits when low voltage, low power or small power-delay products are of concern. It completes and overcomes limitations of previous studies as optimal power-delay curves, for CPL and CMOS full adders, have been constructed using an automatic sizing tool based on statistical optimization. Supply voltages of 3.3 V and 1.5 V have been considered. This study shows that full adders with minimum power consumption are accessible by using the conventional CMOS design style. As a counterpart, minimum delay full adders are obtained with CPL

Keywords

CMOS logic circuits; adders; circuit optimisation; delays; digital arithmetic; logic design; low-power electronics; 1.5 V; 3.3 V; CMOS design style; CMOS full-adder circuits; CPL full-adder circuits; CPTL; LV operation; automatic sizing tool; complementary pass-transistor logic; low voltage adders; low-power logic styles; minimum delay full adders; optimal power-delay curves; statistical optimization; Adders; CMOS logic circuits; Capacitance; Circuit synthesis; Energy consumption; Logic circuits; Logic functions; Low voltage; Noise robustness; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957480

Filename

957480