Title :
Planarized Al processes for sub-half micron VLSI interconnect technology
Author :
Zhao, Bin ; Ting, C.H. ; Ta, L. ; Vasudev, P.K.
Author_Institution :
SAMATECH, Austin, TX
Abstract :
Planarized Al processes have been investigated by electrical measurement and scanning electron microscopy to study their feasibility in building multi-level interconnect structures for VLSI circuits of sub micron geometry. A variety of test structures have been used to characterize these planarized Al processes. It has been demonstrated that 0.35 μm via holes with nearly-vertical side-wall can be filled without using collimated Al deposition. Contact resistance of about 0.3 Ω and specific contact resistivity of approximately 6×10-10 Ω-cm2 were obtained for 0.51 μm vias. Under optimized conditions, very high yield was obtained for both 0.35 μm and 0.5 μm via hole fill
Keywords :
VLSI; aluminium; contact resistance; integrated circuit interconnections; integrated circuit metallisation; scanning electron microscopy; 0.3 ohm; 0.35 micron; 0.5 micron; Al; SEM; VLSI interconnect technology; contact resistance; electrical measurement; multilevel interconnect structures; planarized Al processes; scanning electron microscopy; specific contact resistivity; subhalf micron technology; via hole fill; Buildings; Circuit testing; Collimators; Conductivity; Contact resistance; Electric variables measurement; Geometry; Integrated circuit interconnections; Scanning electron microscopy; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1995 4th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-3062-5
DOI :
10.1109/ICSICT.1995.499267
