Title :
A design methodology to realize delay testable controllers using state transition information
Author :
Iwagaki, Tsuyoshi ; Ohtake, Satoshi ; Fujiwara, Hideo
Author_Institution :
Nara Institute of Science and Technology
Keywords :
Circuit faults; Circuit testing; Clocks; Delay effects; Design methodology; Electrical fault detection; Fault detection; Fault diagnosis; Logic testing; Performance evaluation;
Conference_Titel :
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN :
0-7695-2119-3
DOI :
10.1109/ETSYM.2004.1347655
