Title :
A novel low power multiplexer-based full adder cell
Author :
Alhalabi, Bassem ; Al-Sheraidah, Abdulkarim
Author_Institution :
Dept. of Comput. Sci. & Eng., Florida Atlantic Univ., Boca Raton, FL, USA
fDate :
6/23/1905 12:00:00 AM
Abstract :
A novel low-power multiplexer-based 1-bit full adder cell that uses 12 transistors (MBA-12T) is presented here. MBA-12T is tested along with four other low-power 10-transistor 1-bit full adders that were shown to have more than 26% in power-savings over the conventional 28-transistor CMOS cell. The testing consists of simulating using HSpice under 6 frequencies, and 6 different loads. The testing result shows that the MBA-12T exhibits at least 23% in power-savings over the least power-consuming 10-transistor cell and a minimum of 64% in speed improvement
Keywords :
CMOS logic circuits; adders; circuit simulation; digital arithmetic; low-power electronics; timing; 12 transistor cell; HSpice simulation; dynamic power dissipation; low power full adder cell; multiplexer-based full adder cell; short-circuit current reduction; speed improvement; timing response; Adders; Circuits; Computer science; Explosives; Frequency; Multiplexing; Power engineering and energy; Testing; Throughput; Transistors;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957484
