A neuron MOS transistor-based multiplier cell

Author

Weber, Werner ; Prange, Stefan J. ; Thewes, Roland ; Wohlrab, Erdi

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

fYear

1995

Firstpage

555

Lastpage

558

Abstract

Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications

Keywords

CMOS logic circuits; logic design; multiplying circuits; threshold logic; CMOS-based logic applications; multiplier cell; neuron MOS transistor principle; packing density improvement; threshold logic; CMOS logic circuits; Capacitance; Coupling circuits; Dielectrics; Equations; Logic devices; MOSFETs; Neurons; Nonvolatile memory; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499282

Filename

499282

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1656191