Gaining extra crypto-security using system on chip model for RC5

Author

Elkeelany, Omar ; Olabisi, Adegoke

Author_Institution

Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN

fYear

2006

Firstpage

71

Lastpage

74

Abstract

By exploiting features embedded in modern field programmable gate arrays, which allow system on chip (SoC) modeling, this paper presents a hardware enhanced security for the RC5 encryption system. RC5 algorithm is used as a case study, and the SoC model can apply to similar algorithms. The proposed model is synthesized to FPGA and can easily be mapped to ASIC technology. The proposed model is studied, and has shown improved security against single site physical access attacks. Further simulation studies are undergoing to measure the speed of performance of the proposed model

Keywords

field programmable gate arrays; logic design; private key cryptography; public key cryptography; system-on-chip; ASIC technology; FPGA; RC5 encryption system; crypto-security; field programmable gate arrays; hardware enhanced security; single site physical access attacks; system on chip modeling; Application specific integrated circuits; Computer architecture; Computer security; Explosions; Field programmable gate arrays; Hardware; Public key cryptography; System-on-a-chip; Velocity measurement; Wireless application protocol;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 2006. SSST '06. Proceeding of the Thirty-Eighth Southeastern Symposium on

Conference_Location

Cookeville, TN

Print_ISBN

0-7803-9457-7

Type

conf

DOI

10.1109/SSST.2006.1619080

Filename

1619080