FPGA based on-line complex-number multipliers

This paper proposes two topologies of radix-2 complex-number multipliers based on distributed arithmetic and the redundant signed-digit representation. The advantage of this approach is twofold: the distributed arithmetic reduces the hardware requirements respect to direct implementation of the complex-number multiplication, and the redundant number system avoids the carry-propagation and allows computing on-line the digits. Two Radix-2 architectures are presented. These multipliers have been implemented on FPGA and an optimum mapping is proposed. The presented circuits have been compared to other complex-number multipliers leading to more efficient area-time structures and a lower latency