Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping

This paper presents the modeling and design consideration of a time-based ADC architecture that uses VCOs in a high-linearity, 2^nd-order noise-shaping delta-sigma ADC. Instead of driving the VCO by a continuous analog signal, which suffers from the nonlinearity problem of the VCO gain, the VCO is driven in an intrinsically linear way, by a time-domain PWM signal. The two discrete levels of the PWM waveform define only two operating points of the VCO, therefore guaranteeing linearity. In addition, the phase quantization error between two consecutive samples is generated by a phase detector and processed by a second VCO. Together with the output of the first VCO, a MASH 1-1 2^nd-order noise-shaping VCO-based time-domain delta-sigma converter is obtained. Fabricated in 90 nm CMOS technology, the SFDR is larger than 67 dB without any calibration for a 20 MHz bandwidth.