Prospects for pipeline in high-density magnetic field-coupled logic

Clock is fundamental to information flow in magnetic field-coupled logic. And to improve the throughput from magnetic field-coupled logic, the logic operation also needs to be pipelined. However, pipeline implemented with the existing clocking structure of magnetic logic generates a constraint on layout and overall area. In this paper we have discussed this constraint and possible solutions to this problem with the help of multiphase clock and CMOS integration. The solution is a tradeoff between throughput, logic density, hardware complexity and latency.