• DocumentCode
    165645
  • Title

    Ant-Colony-Optimization based heuristic searching algorithm for cell assignment in a hybrid CMOS/nano circuits (CMOL) array

  • Author

    Chong Xu ; Nepal, Kundan

  • Author_Institution
    Sch. of Eng., Univ. of St. Thomas, St. Paul, MN, USA
  • fYear
    2014
  • fDate
    18-21 Aug. 2014
  • Firstpage
    262
  • Lastpage
    267
  • Abstract
    In this paper, we focus on the placement of cells in a CMOL array given a specific connectivity domain using the Ant Colony Optimization algorithm. We describe the algorithm and using example circuit show that our approach provides a better placement than other recent work in terms of the number of buffers needed.
  • Keywords
    CMOS integrated circuits; ant colony optimisation; circuit optimisation; logic arrays; nanoelectronics; search problems; CMOL; ant-colony-optimization based heuristic searching algorithm; buffers; cell assignment; hybrid CMOS-nanocircuit array; specific connectivity domain; CMOS integrated circuits; Computer architecture; Field programmable gate arrays; Logic gates; Microprocessors; Nanoscale devices; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nanotechnology (IEEE-NANO), 2014 IEEE 14th International Conference on
  • Conference_Location
    Toronto, ON
  • Type

    conf

  • DOI
    10.1109/NANO.2014.6968071
  • Filename
    6968071
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=165645