Design of a high-speed (255,239) RS decoder using 0.18 μm CMOS

Author

Dinh, Anh ; Teng, Daniel

Author_Institution

Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada

Volume

4

fYear

2004

Firstpage

2171

Abstract

Reed-Solomon (RS) codes have been widely used in a variety of communication systems and data storages to protect digital data against errors occurring in the transmission process. This paper presents a VLSI implementation of a high-speed, 8-error correcting, RS(255,239) decoder in the 0.18 μm CMOS technology. The decoder architecture uses the "division-free algorithm", a modified Berlekamp-Massey algorithm, in the key equation solver and a terminated mechanism in the Chien search circuit. The other key in this implementation is the use of highly efficiently simplified Galois field arithmetic operation circuits. The low-complexity, low latency power-sum and inversion circuits boost up the speed and latency of the decoder. The chip occupies a core area of 1.5 mm² and obtains a data processing rate exceeding 1 Gbit/s.

Keywords

CMOS integrated circuits; Galois fields; Reed-Solomon codes; VLSI; decoding; error correction codes; (255,239) RS decoder; 0.18 micron; CMOS; Chien search circuit; Galois field arithmetic operation; Reed-Solomon codes; VLSI implementation; division-free algorithm; error correcting decoder; high-speed RS decoder; low latency power-sum circuits; low-complexity inversion circuits; modified Berlekamp-Massey algorithm; CMOS technology; Circuits; Decoding; Delay; Equations; Galois fields; Memory; Protection; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1347674

Filename

1347674