Dynamic aging of CMOS SOI transistors in circuit operation

SOI transistors, operating in dynamic mode, have been fully investigated using dedicated test circuits. Indeed, specific circuits have been built in order to make, in-situ monitoring of electrical characteristics of n- and p-MOSFETs. We have demonstrated that physical mechanisms of the degradation, in partially depleted SOI devices, are comparable after static and dynamic stress. Indeed, back interface degradation analysis has revealed that, even after dynamic aging, p-MOSFETs are submitted to electron trapping while it is not the case for n-MOSFETs. The “quasi static” approach is not applicable in inverter-type circuit, and could be explained by successive injection of holes and electrons due to the specific bias waveform, leading to an enhancement of the degradation