Threshold tuning method for arrays of split-gate nanostructure transistors in series

Author

Al-Taie, Haider ; Smith, Luke W. ; Puddy, Reuben K. ; See, Patrick ; Griffiths, Jonathan P. ; Farrer, I. ; Jones, Geb A. C. ; Ritchie, D.A. ; Smith, Charles G. ; Kelly, Michael J.

Author_Institution

Dept. of Eng., Univ. of Cambridge, Cambridge, UK

fYear

2014

fDate

18-21 Aug. 2014

Firstpage

490

Lastpage

493

Abstract

This paper presents a method to tune an arbitrary number of split-gate transistors in series to their threshold voltage, prior to initiating any particular experiment. The model accounts for device variations and considers coupled/uncoupled electrical gates and ballistic/ohmic addition of resistances. Experimental verification of this `zeroing method´ is provided by detailed conductance measurements through a two-dimensional electron gas formed in a GaAs/AlGaAs heterostructure with two split-gate transistors in series and is extended to zero an array of up to nine split gates in series.

Keywords

III-V semiconductors; aluminium compounds; gallium arsenide; nanoelectronics; semiconductor device models; transistors; two-dimensional electron gas; GaAs-AlGaAs; ballistic-ohmic resistance; conductance measurements; coupled-uncoupled electrical gates; device variations; split-gate nanostructure transistor arrays; threshold tuning method; threshold voltage; two-dimensional electron gas; zeroing method; Gallium arsenide; HEMTs; Logic gates; MODFETs; Split gate flash memory cells; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Nanotechnology (IEEE-NANO), 2014 IEEE 14th International Conference on

Conference_Location

Toronto, ON

Type

conf

DOI

10.1109/NANO.2014.6968100

Filename

6968100