Title :
Bipolar installed CMOS technology without any process step increase for high speed cache SRAM
Author :
Ishimaru, K. ; Takahashi, M. ; Nishigohori, M. ; Okayama, Y. ; Unno, Y. ; Matsuoka, F. ; Kakumu, M.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
Double-polysilicon self-aligned bipolar transistor was installed to the CMOS process without any process step increase. The collector region and n-well were fabricated simultaneously by ion implantation. Gate self-aligned contact technique for 6T memory cell was applied for bipolar emitter contact. Obtained bipolar transistor characteristics were sufficient for current-sense amplifier use, which can realize low cost and high performance L2 cache SRAM
Keywords :
BiCMOS memory circuits; SRAM chips; cache storage; ion implantation; BiCMOS technology; Si; bipolar installed CMOS technology; collector region; current-sense amplifier; double-polysilicon self-aligned bipolar transistor; gate self-aligned contact technique; high speed cache SRAM; ion implantation; n-well; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Costs; Delay effects; Delay lines; Fabrication; Ion implantation; Random access memory;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499309
