Title :
AUTODDM: automatic characterization tool for the delay degradation model
Author :
Juan-Chico, J. ; Bellido, M.J. ; Ruiz-de-Clavijo, P. ; Baena, C. ; Valencia, M.
Author_Institution :
Instituto de Microelectron. de Sevilla, CNM, Seville, Spain
fDate :
6/23/1905 12:00:00 AM
Abstract :
As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which it is necessary to face in order to achieve a practical implementation of the model. In this way, this paper describes the characterization process associated with the previously developed delay degradation model for CMOS logic gates (DDM) and the implementation of an automatic characterization tool that automates the process and allows easy and fast model parameter extraction
Keywords :
CMOS logic circuits; circuit simulation; delays; integrated circuit modelling; logic simulation; timing; AUTODDM automatic characterization tool; CMOS logic gates; automatic characterization tool; characterization process; delay degradation model; delay model complexity; delay models; logic timing simulation; model parameter values extraction; model parameters extraction; Automatic logic units; CMOS logic circuits; CMOS process; Degradation; Delay; Distributed decision making; Logic gates; Parameter extraction; Semiconductor device modeling; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957531
