Title :
A mixed-mode delay-locked loop for wide-range operation and multiphase clock generation
Author :
Cheng, Kuo-Hsing ; Lo, Yu-Lung ; Yu, Wen-Fang ; Hung, Shu-Yin
Author_Institution :
Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
Abstract :
This paper describes a mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs with just one clock cycle. The architecture of the proposed DLL uses the mixed-mode time-to-digital converter (TDC) scheme for phase range selector to offer faster locking time. The multi-controlled delay cell for voltage-controlled delay line (VCDL) was used to provide wide locked range and the low-jitter performance. The proposed DLL can solve the problem of the false locking associated with conventional DLLs. The circuit design and HSPICE simulation are based upon TSMC 0.258 μm 1P5M N-well CMOS process with a 2.5 V power supply voltage. The post-layout simulation results show that the proposed DLL has wide locking range 50 to 280 MHz. Moreover, the total time delay from all delay stages is precisely one period of the input reference signal, and that can generate equally spaced ten-phase clocks.
Keywords :
CMOS integrated circuits; SPICE; delay lines; delay lock loops; integrated circuit design; mixed analogue-digital integrated circuits; 0.25 micron; 2.5 V; 50 to 280 MHz; HSPICE simulation; TSMC 0.25 μm 1P5M N-well CMOS process; VCDL; circuit design; clock cycle; delay-locked loop; false locking; locked range; locking time; mixed-mode DLL; mixed-mode TDC; multi-controlled delay cell; multiphase clock generation; phase range selector; time delay; time-to-digital converter; voltage-controlled delay line; wide-range operation; Capacitors; Circuit simulation; Clocks; Delay effects; Delay lines; Filters; Frequency; Phase locked loops; Signal generators; Voltage;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
DOI :
10.1109/IWSOC.2003.1213012
