Lead compensation to improve the stability of a two stage rail-to-rail CMOS opamp

Author

Delage, Jean-François ; Sawan, Mohamad

Author_Institution

Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

561

Abstract

The design issues of a two-stage rail-to-rail operational amplifier are discussed in this paper. Current regulation during common mode voltage sweep allows us to apply a lead compensation technique, and a simple scheme enables temperature and process variation robustness. This compensation involves 15 degrees improvement in the phase margin when resistive elements are introduced in the compensation path. The proposed opamp has been implemented and measurements show a 10.4 MHz unity gain bandwidth (GBW) with a minimal phase margin of around 54° for a capacitive load of 35 pF. In addition, a slew rate of about 14 V/μs is attained and the current consumption is maintained below 530 μA

Keywords

CMOS analogue integrated circuits; circuit stability; compensation; integrated circuit design; operational amplifiers; 0.35 micron; 10.4 MHz; 35 pF; 530 muA; CMOS opamp; capacitive load; common mode voltage sweep; compensation path; current consumption; current regulation; design issues; lead compensation technique; minimal phase margin; phase margin; process variation robustness; resistive elements; slew rate; temperature variation robustness; two-stage rail-to-rail operational amplifier; unity gain bandwidth; Current control; Gain measurement; Operational amplifiers; Phase measurement; Rail to rail amplifiers; Rail to rail operation; Robustness; Stability; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957538

Filename

957538