DocumentCode
1657458
Title
A catalog of hardware acceleration techniques for real-time reconfigurable system on chip
Author
Bergmann, Neil ; Waldeck, Peter ; Williams, John
Author_Institution
Queensland Univ., Brisbane, Qld., Australia
fYear
2003
Firstpage
112
Lastpage
115
Abstract
The new technology of reconfigurable System-on-Chip is shown to be a good match to the requirements of real-time embedded systems. In particular, the judicious use of specialized data processing peripherals can reduce the CPU load significantly and greatly ease the task of guaranteeing that real-time deadlines are met in complex multiprocessing real-time systems. A catalog of other possible uses for the reconfigurable logic resources on such a chip which can assist in improving real-time system performance is also presented.
Keywords
embedded systems; field programmable gate arrays; integrated circuit design; logic design; real-time systems; reconfigurable architectures; system-on-chip; CPU load; data processing peripheral; embedded system; hardware acceleration technique; reconfigurable logic resource; reconfigurable system on chip; Acceleration; Delay; Embedded system; Field programmable gate arrays; Hardware; Microcontrollers; Pulse width modulation; Read only memory; Real time systems; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN
0-7695-1944-X
Type
conf
DOI
10.1109/IWSOC.2003.1213017
Filename
1213017
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