A high speed multi-input comparator with clocking-charge based for low-power systems

Author

Hsia, Shih-Chang

Author_Institution

Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Taiwan

fYear

2003

Firstpage

130

Lastpage

133

Abstract

Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4×6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm² using UMC 0.5 μm process.

Keywords

CMOS digital integrated circuits; clocks; comparators (circuits); digital signal processing chips; integrated circuit design; low-power electronics; 4 bit; CMOS base; Spice simulator; clocking-charge; comparison function; comparison-cell; complementary metal oxide semiconductor; discrete signal processing; low-power system; multi-input comparator; prototype cell; Adders; CMOS logic circuits; Circuit synthesis; Clocks; Complexity theory; Delay effects; Design automation; Signal processing; Very large scale integration; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Print_ISBN

0-7695-1944-X

Type

conf

DOI

10.1109/IWSOC.2003.1213021

Filename

1213021