Title :
New embedded memory architecture for enhanced yield, performance and power consumption
Author :
Polianskikh, Boris ; Zilic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, Que., Canada
fDate :
6/23/1905 12:00:00 AM
Abstract :
A new cross-shared redundancy (CSR) architecture of embedded memory for yield improvement is proposed. The model of CSR takes into account cluster errors, which are common for deep-submicron technologies. The redundancy scheme is optimized in consideration of low-power and fast operation. A yield model of cross-shared redundancy for the embedded memory is presented
Keywords :
VLSI; application specific integrated circuits; integrated circuit design; integrated circuit yield; low-power electronics; memory architecture; redundancy; SOCs; cluster errors; cross-shared redundancy architecture; deep-submicron technologies; embedded memory architecture; low-power operation; power consumption; yield improvement; CMOS technology; Capacitance; Computer errors; Energy consumption; Hardware; Memory architecture; Protection; Redundancy; Semiconductor device modeling; Wire;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957544
