Comparison of Reed-Solomon decoder implementations based on two different microprocessors

The implementation of the (63, 43) RS decoder on two simple and inexpensive microprocessor chips, the Intel 8749 and the Zilog Z-80, is discussed. A frequency-domain decoding algorithm that consists of a Fourier transform module followed by the Berlekamp-Massey and recursive extensive modules is used. The choice of a code length of 63 symbols and an error correction capacity of 10 symbols are dictated by the memory restrictions of the 8749. To achieve a fast data rate while keeping the error correction capability at an acceptable level, memory utilization and arithmetic should be as efficient as possible. In the 8749, multiplications are based on log/antilog tables, whereas the Z-80 has a large enough memory space to support the storage of a full multiplication table