Two-dimensional array layout for NMOS 4-phase dynamic logic

Author

Furuie, Makoto ; Onoye, Takao ; Tsukiyama, Shuji ; Shirakawa, Isao

Author_Institution

Dept. of Inf. Syst. Eng., Osaka Univ., Japan

Volume

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

589

Abstract

A novel layout approach of array cell (AC) architecture is described, which is dedicated to nMOS 4-phase dynamic logic. An AC is constructed of (M×N)+2 nMOSFETs which constitute each type of nMOS 4-phase logic gates. A graph theoretic approach to the nMOSFET placement in conjunction with a simulated annealing procedure is exploited for the area reduction in the layout design of the AC. A number of experimental results demonstrate the practicability of the proposed approach

Keywords

MOS logic circuits; cellular arrays; circuit layout CAD; graph theory; integrated circuit layout; logic CAD; logic arrays; logic gates; simulated annealing; area reduction; array cell architecture; graph theoretic approach; layout design; logic gates; nMOS 4-phase dynamic logic; nMOSFET placement; simulated annealing procedure; CMOS logic circuits; Clocks; Delay; Electronic mail; Frequency; Logic arrays; Logic functions; Logic gates; MOS devices; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957545

Filename

957545

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1657615