Title :
Low-power FFT/IFFT VLSI macro cell for scalable broadband VDSL modem
Author :
Saponara, S. ; Serafini, L. ; Fanucci, L.
Author_Institution :
Dept. of Inf. Eng., Pisa Univ., Italy
Abstract :
The cost-effective realization of forward/inverse Fast Fourier Transform (FFT/IFFT) in Digital Subscriber Line (DSL) systems is addressed in the paper. A processor based on a FFT/IFFT cascade architecture plus pre/postprocessing stages is discussed and characterized from the high-level choices down to gate-level synthesis. The effects of supply voltage scaling on power consumption and circuit performance are examined, as well as the use of different target technologies. Low-power design techniques, based on clock gating and data driven switching activity reduction, further decrease the energy consumption. Synthesis results in a 0.18 μm CMOS technology show that the processor is suitable for real-time modulation/demodulation in scalable VDSL systems with a power consumption of few tens of mW.
Keywords :
CMOS integrated circuits; VLSI; digital subscriber lines; fast Fourier transforms; integrated circuit design; low-power electronics; modems; power consumption; system-on-chip; 0.18 micron; CMOS technology; FFT/IFFT VLSI macro cell; clock gating; data driven switching activity; forward inverse fast Fourier transform; gate-level synthesis; power consumption; scalable broadband VDSL modem; supply voltage scaling; very high-rate digital subscriber line; CMOS technology; Circuit optimization; Circuit synthesis; Clocks; DSL; Energy consumption; Fast Fourier transforms; Modems; Very large scale integration; Voltage;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
DOI :
10.1109/IWSOC.2003.1213027
