High level modeling and simulation of a VDSL modem in SystemC 2.0-IPsim

Author

Armaroli, Armando ; Coppola, Marcello ; Nava, Mario Diaz ; Fanucci, Luca

Author_Institution

DEIT, Pisa Univ., Italy

fYear

2003

Firstpage

175

Lastpage

180

Abstract

In order to deal with present System on Chip design complexity and short time to market, system level specification/verification techniques and reusable Intellectual Property cores are key factors. To this aim, system level C++ object oriented methodology named IPsim has been developed as a C++ library on top SystemC 2.0. In this paper, the IPsim modeling and simulation of a VDSL modem is presented. Moreover, quantitative comparison between IPsim and behavioral VHDL simulation speed is also performed.

Keywords

C++ language; digital simulation; digital subscriber lines; hardware description languages; high level synthesis; industrial property; modelling; modems; object-oriented programming; system-on-chip; C++ library; C++ object oriented methodology; IPsim modeling; SystemC 2.0; VDSL modem; VHDL simulation; high level modeling; intellectual property core; system level specification; system level verification; system on chip design; very high speed integrated circuit hardware description language; very high-rate digital subscriber line; Electronic design automation and methodology; Embedded software; Hardware; Intellectual property; Modems; Object oriented modeling; Software tools; System-on-a-chip; Time to market; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on

Print_ISBN

0-7695-1944-X

Type

conf

DOI

10.1109/IWSOC.2003.1213030

Filename

1213030