DocumentCode
1657966
Title
The noise immunity for the low voltage logic circuits
Author
Golumbeanu, V. ; Svasta, P. ; Leonescu, D.
Author_Institution
Bucharest Univ., Romania
Volume
1
fYear
1998
Firstpage
116
Abstract
The authors present the general relation for the determination of the dynamic noise immunity for the interconnection of two digital circuits. They present the relations for determination of the parameters of the guaranteed and typical noise immunity: the amplitude of the voltage, duration (time), rise and fall time, phase difference, power and energy. For the low voltage logic circuit subfamilies (LV, LVC, LVT, ALVC) the parameters of guaranteed and typical noise immunity are calculated
Keywords
CMOS logic circuits; electromagnetic compatibility; electromagnetic interference; integrated circuit noise; CMOS logic circuits; EMC; EMI; digital circuits interconnection; dynamic noise immunity; electromagnetic compatibility; guaranteed noise immunity; low voltage logic circuits; Circuit noise; Digital circuits; Electromagnetic compatibility; Electromagnetic interference; Immunity testing; Integrated circuit interconnections; Logic circuits; Low voltage; Noise level; Phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrotechnical Conference, 1998. MELECON 98., 9th Mediterranean
Conference_Location
Tel-Aviv
Print_ISBN
0-7803-3879-0
Type
conf
DOI
10.1109/MELCON.1998.692351
Filename
692351
Link To Document