Title :
The implementation of 100MHz data acquisition based on FPGA
Author :
Lin, Tao ; Zhengou, Zhou
Author_Institution :
Southwest China Res. Inst. of Electron., Chengdu, China
Abstract :
A high-speed data acquisition based on FPGA and implemented in VHDL is presented in this paper. According to the requirement of a new radar system, several new technologies are adopted in the design and implementation such as time compression storage and memory rewriting. As a result, the system performs well with low dissipation of power, simple circuit layout and high efficient utilization of memory. The acquisition system comprises four parts: ADC circuit, data package and interface, sampling data memory and data flag memory. To implement large circuit, FPGA is adopted in this data acquisition system with reconfigurable ability and constant delay feature according to Z.G. Vranesic (1999).
Keywords :
data acquisition; field programmable gate arrays; hardware description languages; radar; reconfigurable architectures; 100 MHz; ADC circuit; FPGA; VHDL implementation; constant delay feature; data acquisition; data flag memory; data interface; data package; efficient memory utilization; low power dissipation; memory rewriting; reconfigurable ability; sampling data memory; simple circuit layout; time compression storage; Circuits; Data acquisition; Electromagnetic radiation; Field programmable gate arrays; Frequency; Pulse modulation; Radar; Sampling methods; Signal analysis; Signal processing;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
DOI :
10.1109/IWSOC.2003.1213050
