A contention-alleviated static keeper for high-performance domino logic circuits

Author

Shieh, Shang-Jyh ; Wang, Jinn-Shyan ; Yeh, Yuan-Hsun

Author_Institution

Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

707

Abstract

The domino logic circuit is popular in high performance VLSI chips. A feedback keeper is usually used to overcome the charge sharing problem in the domino circuit. In this paper, a contention-alleviated static keeper (CASK) is proposed. The key idea is to reduce the contention between the pull-down network and the feedback keeper by lowering the gate voltage of the keeper. By using the CASK technique, better performance can be achieved, in addition to maintained noise robustness, with smaller sizing factor. By tuning the gate-bias voltage to the feedback PMOS, the proposed keeper is suitable for domino circuits with a range of supply voltage. Additionally, the CASK has been demonstrated to enhance the performance of low-power low swing domino circuits, and the results show that delay and power can be reduced by 26% and 11%, respectively

Keywords

CMOS logic circuits; delays; integrated circuit design; logic design; low-power electronics; charge sharing problem; contention-alleviated static keeper; delay reduction; domino CMOS circuit; domino logic circuits; feedback PMOS; feedback keeper; gate voltage; gate-bias voltage tuning; high-performance VLSI chips; low-power low-swing domino circuits; noise robustness; power reduction; pull-down network; sizing factor; Circuit noise; Coupling circuits; Delay; Feedback circuits; Inverters; Logic circuits; MOSFETs; Noise robustness; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957573

Filename

957573