VHDL-based development of a 32-bit pipelined RISC processor for educational purposes

This paper describes the ongoing activities in design education at the University of Stuttgart. It is decomposed into two steps. The first step is a course of one semester. There the students obtain basic design and architecture knowledge under the close guidance of an experienced advisor. For the second step, we have launched a little project, that comes as close as possible to real life experience: the design of the DLX, a 32-bit RISC processor. The project has been split into smaller tasks being handled autonomously by the students in a six months period. As a side effect a complete processor model is developed