DocumentCode :
1658416
Title :
Analysis of coupling noise in dynamic circuit
Author :
Chowdhury, Masud H. ; Ismail, Yehea I.
Author_Institution :
Electr. & Comput. Eng., Northwestern Univ., Evaston, IL, USA
fYear :
2003
Firstpage :
320
Lastpage :
325
Abstract :
Noise has become an important metric of deep submicron digital integrated circuit performance, and is becoming even more prominent due to the increasing usage of noise sensitive dynamic circuits for speed and area requirements. This paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits to analyze the effects of coupling, which is considered as the dominant source of noise. These solutions are within 5% of dynamic simulations. It is shown that not all the scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuit. Most of the work treated noise immunity and the noise content separately. This paper introduces a positive analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.
Keywords :
electric noise measurement; integrated circuit noise; integrated circuit reliability; coupling noise analysis; deep submicron; digital integrated circuit; dynamic circuit; dynamic simulations; noise content; noise immunity; noise scalability; noise sensitive dynamic circuits; noise tolerance metrics; CMOS logic circuits; CMOS technology; Circuit noise; Coupling circuits; Dynamic voltage scaling; Frequency; Integrated circuit noise; Inverters; Noise level; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
Type :
conf
DOI :
10.1109/IWSOC.2003.1213056
Filename :
1213056
Link To Document :
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