Title :
A process technology for 1 giga-bit DRAM
Author :
Lee, K.P. ; Park, Y.S. ; Ko, D.H. ; Hwang, C.S. ; Kang, C.J. ; Lee, K.Y. ; Kim, J.S. ; Park, J.K. ; Roh, B.H. ; Lee, J.Y. ; Kim, B.C. ; Lee, J.H. ; Kim, K.N. ; Park, J.W. ; Lee, J.G.
Author_Institution :
Semicond. R&D Centre, Samsung Electron. Co. Ltd., Kyungki-Do, Japan
Abstract :
In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi x gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO3 (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond
Keywords :
DRAM chips; ULSI; capacitors; dielectric thin films; integrated circuit technology; isolation technology; (BaSr)TiO3; 1 Gbit; DRAM; TiSi; dielectric material; giga bit density technology; next generation memory devices; process technology; self aligned contact; shallow trench isolation; stack capacitor cell; Binary search trees; Capacitors; Etching; Isolation technology; MOS devices; Manufacturing processes; Optical control; Random access memory; Scalability; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499363
