Title :
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits
Author :
Perri, S. ; Corsonello, P. ; Cocorullo, G. ; Cappuccino, G. ; Staino, G.
Author_Institution :
Dept. of Electronics, Comput. Sci. & Syst., Calabria Univ., Italy
fDate :
6/23/1905 12:00:00 AM
Abstract :
Self-timed adders are widely used since they compute in mean time. Traditionally, in order to achieve very high-speed performance they are realized using dynamic CMOS logic (Domino, DCVSL). However, recent works have demonstrated that efficient self-timed adders can also be realized using fully static CMOS circuits. In this paper, a new high-performance fully static 56-bit self-timed adder is presented. The proposed VLSI implementation uses overlapped execution circuits, which perform their computation by exploiting the initialization time elapsing between two consecutive operations. The new adder realized with AMS 0.6 μm CMOS standard-cells shows an average addition time of ~3.3 ns, requires ~900000 μm2 of silicon area and consumes a maximum power of ~660 mW @300 MHz
Keywords :
CMOS logic circuits; VLSI; adders; circuit simulation; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; 0.6 micron; 3.3 ns; 300 MHz; 56 bit; 660 mW; CMOS standard-cells; DCVSL dynamic CMOS logic; Domino dynamic CMOS logic; VLSI implementation; average addition time; consecutive operations; dynamic CMOS logic; fully static CMOS self-timed adder; initialization time; maximum power consumption; mean time computing; overlapped execution circuits; self-timed adders; silicon area; static CMOS circuits; very high-speed performance; Adders; CMOS logic circuits; Computer science; Councils; Lab-on-a-chip; Libraries; Mathematics; Power dissipation; Silicon; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957577
