Abstract :
In this communication, a strategy to design fast multiplexers with high fan in is proposed. It is based on the recently proposed architecture heterogeneous tree (Lin, IEEE Trans. on CAS, pt. I, vol. 19, no. 18, pp. 963-967, 2000), which until now has been optimized assuming only CMOS switch-based implementation with transmission gates or pass transistors. In this work the design strategy of heterogeneous-tree multiplexers is extended to the case of switches with driving capability, like clocked inverters. It provides design criteria to minimize the delay, which are general and simple to be applied, and thus are helpful from the early design phases. Moreover, performance achievable is analytically expressed for a given fan in and CMOS process. As an example, a multiplexer designed with the strategy proposed and with a fan in of 256 is simulated using a 0.35-μm CMOS process. The predicted delay agrees well with the simulated value
Keywords :
CMOS logic circuits; circuit simulation; delays; integrated circuit design; logic CAD; logic gates; logic simulation; multiplexing equipment; 0.35 micron; CMOS process; CMOS switches; clocked inverters; delay; delay minimization; design criteria; design phases; design strategy; heterogeneous tree architecture; heterogeneous-tree multiplexers; high fan-in multiplexers; multiplexer design; multiplexer design strategy; multiplexer simulation; optimized design; pass transistors; switch driving capability; switches; transmission gates; CMOS process; Clocks; Communication switching; Content addressable storage; Delay; Design optimization; Inverters; Multiplexing; Performance analysis; Switches;
