Title :
High performance 0.25 μm SRAM technology with tungsten interpoly plug
Author :
McNelly, T.F. ; Hayden, J.D. ; Perera, AH ; Pfiester, J.R. ; Subramanian, C.K. ; Blackwell, M. ; James, B. ; Ajuria, S. ; Fell, W. ; Ku, Y.C. ; Lii, T. ; Lin, J.-H. ; Nkansah, F. ; Philbin, C. ; Sun, C.J. ; Thompson, M. ; Woo, M.
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
Abstract :
A high performance 0.25 μm CMOS process has been developed for fast static RAMs, featuring retrograde wells, shallow trench isolation with 0.55 μm active pitch, a 55 Å nitrided gate oxide, 0.25 μm polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 μA/μm respectively at an off-leakage of 10 pA/μm, overgated TFTs with an on/off ratio greater than 6·10 5, stacked capacitors for improved SER, five levels of polysilicon planarized by chemical-mechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 μm contacts and a 0.625 μm metal pitch. A split word-line bitcell was scaled to an area of 3.74 μm2 using 0.25 μm design rules
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit metallisation; isolation technology; tungsten; 0.25 micron; CMP; SRAM technology; Si; W; W interpoly plug; chemical-mechanical polishing; fast static RAMs; high performance CMOS process; nitrided gate oxide; overgated TFTs; polycide gate; retrograde wells; self-aligned interpoly contacts; shallow trench isolation; split word-line bitcell; stacked capacitors; surface channel NMOS transistors; surface channel PMOS transistor; CMOS process; CMOS technology; Capacitors; Chemical processes; Isolation technology; MOS devices; MOSFETs; Random access memory; Thin film transistors; Tungsten;
Conference_Titel :
Electron Devices Meeting, 1995. IEDM '95., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-2700-4
DOI :
10.1109/IEDM.1995.499368
