Test pattern generator for hybrid testing of combinational circuits

A novel test pattern generator for the built-in self-test technique in testable combinational circuits is proposed. The presented solution is based on a hybrid testing reconfigurable test pattern generator, that uses a shift register reacted through two different networks: it firstly reproduces a pseudo-random sequence of test patterns using a linear feedback combinational network and then reproduces deterministic precalculated test patterns, useful to detect hard faults, using a nonlinear feedback combinational network. For the proposed approach, a synthesis tool (based on state space heuristic search and the "selfish gene" genetic algorithm) able to determine test pattern generator for a given test set, is also proposed. Experiments to evaluate synthesis time and the test sequence length are conducted on well-known ISCAS\´85 circuits. Comparison with previous techniques shows the effectiveness of proposed solution