Memory efficient pipelined Viterbi decoder with look-ahead trace back

This paper presents a pipelined Viterbi decoder architecture with look-ahead Trace Back (TB). The pipelined architecture is one of the best choices for high throughput of the Viterbi decoder but requires high hardware complexity. The novel architecture is proposed to reduce the hardware complexity based on look-ahead TB concept in the Viterbi decoder. In the proposed architecture, the TB process is carried out at each stage instead of doing it after the definite stages. Thus, the novel architecture does not need the TB block in the conventional Viterbi decoder and has considerably less hardware complexity. Experimental results show that more than 60% memory can be reduced when the look-ahead TB architecture is used for Viterbi decoder with code rate R=1/2 and constraint length K=7