High voltage BiCDMOS technology on bonded 2 μm SOI integrating vertical npn pnp, 60 V-LDMOS and MPU, capable of 200°C operation

Author

Funaki, Hideyuki ; Yamaguchi, Yoshihiro ; Kawaguchi, Yusuke ; Terazaki, Yoshinori ; Mochizuki, Hiroshi ; Nakagawa, Akio

Author_Institution

Mater. & Devices Res. Labs., Toshiba Corp., Kawasaki, Japan

fYear

1995

Firstpage

967

Lastpage

970

Abstract

Trench isolated 60 V BiCDMOS processes on bonded 2 μm thick SOI, capable of integrating 60 V low on-resistance lateral DMOS, vertical npn and pnp, and an MPU have been developed. 200°C high temperature operation has been demonstrated. The processes are completely compatible with the conventional 0.8 μm rule CMOS processes, and are capable of integrating any existing library of MPUs, logic and analog circuits together with 6O V DMOS H bridges

Keywords

BiCMOS integrated circuits; isolation technology; power integrated circuits; silicon-on-insulator; 2 mum; 200 C; 60 V; CMOS process compatibility; DMOS H bridges; LDMOS; MPU library integration; bonded SOI; high voltage BiCDMOS technology; low on-resistance lateral DMOS; trench isolated BiCDMOS processes; vertical npn pnp integration; Analog circuits; Bridge circuits; CMOS logic circuits; CMOS process; CMOS technology; Clocks; FETs; Temperature; Voltage; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1995. IEDM '95., International

Conference_Location

Washington, DC

ISSN

0163-1918

Print_ISBN

0-7803-2700-4

Type

conf

DOI

10.1109/IEDM.1995.499377

Filename

499377