Title :
Formal verification of digital circuits by 3-valued simulation
Author :
Wahba, Ayman M. ; Aas, Einar J.
Author_Institution :
Mentor Graphics, Egypt
fDate :
6/23/1905 12:00:00 AM
Abstract :
A new technique for digital circuit verification is presented. The new technique is based on the 3-value simulator, 3 VS. Our motivation for utilizing 3 VS is the desire to bridge the gap between common industrial practice of verification through simulation, and the world of formal verification. A metric for verification coverage is defined, and it is shown to provide a lower bound of design confidence. 3 VS and OBDD-based formal verification are compared, and none of the methods is declared generally superior
Keywords :
circuit simulation; digital integrated circuits; formal verification; logic CAD; 3-value simulator; 3VS; digital circuit verification; formal verification; three-valued simulation; verification coverage metric; Boolean functions; Bridge circuits; Circuit simulation; Design methodology; Digital circuits; Digital systems; Formal verification; Graphics; Logic design; Terminology;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957592
