Title :
VLSI architectures for blind equalization based on fractional-order statistics
Author :
Paliouras, V. ; Dagres, J. ; Tsakalides, P. ; Stouraitis, T.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
fDate :
6/23/1905 12:00:00 AM
Abstract :
Four types of VLSI architectures for the hardware realization of the FLOS-CM algorithm are introduced in this paper. Each architecture is appropriate for a particular environment. The FLOS-CM algorithm is found to be amenable for implementation using logarithmic arithmetic. A logarithmic architecture is shown to require up to 50% less area and be 14% faster than a linear fixed-point arithmetic counterpart. In terms of Area×Time and Area×Time2 complexities, the logarithmic architecture is up to 120% better
Keywords :
VLSI; blind equalisers; computer architecture; digital arithmetic; digital signal processing chips; statistics; FLOS-CM algorithm; VLSI architectures; alpha-stable noise model; blind equalization; complexities; fractional-order statistics; hardware realization; logarithmic architecture; logarithmic arithmetic; 1f noise; Additive noise; Blind equalizers; Computer architecture; Degradation; Fixed-point arithmetic; Gaussian noise; Intersymbol interference; Statistics; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957595
