Design of a high speed, low power synchronously clocked NOR-based JK flip-flop using modified GDI technique in 45nm technology

The current paper aims to put forward the arrangement of a new high speed, low power synchronously clocked NOR-based JK flip-flop embracing modified Gate Diffusion Input (GDI) procedure in 45nm technology. The propounded design on comparison with a synchronously clocked NOR-based JK flip-flop employing the traditional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL), respectively showed a considerable amount of reduction in delay time, average power consumption (P_avg) along with Power Delay Product (PDP). Delay time is found to be as low as 2.42nano second while P_avg is as low as 11.19μW thereby giving a PDP as low as 2.71 × 10^-14 Joule for 0.9 volt power supply. Furthermore there is a remarkable contraction in transistor count compared to conventional synchronously clocked NOR-based JK flip-flop comprising CMOS transistors, transmission gates and CPL, accordingly suggesting minimization of area. The simulation of the proposed design has been carried out in Tanner SPICE and the layout has been designed in Microwind.